Power converters and associated methods of operation

ABSTRACT

Power converters and associated methods of operation are disclosed herein. In one embodiment, a power converter includes a first switch and a second switch electrically coupled to the first switch in series. The first switch is electrically coupled to a first node and to a second node via the second switch. The power converter further includes a capacitor and a third switch electrically coupled to the first node and to the second node via the capacitor and the second switch. The third switch has a linear-active region of operation.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Chinese patent application No. 200810045718.7, filed Aug. 1, 2008, which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to power converters and associated methods of operation. More particularly, the present disclosure relates to DC-DC converters and associated methods of operation.

BACKGROUND

Converters are commonly used in many of today's electronic equipment for converting a supply voltage to an output voltage. Important performance factors for such converters are output voltage ripples and noises. One conventional technique utilizes a boost circuit in the converters. The boost circuits may have a low voltage ripple and low noise. However, such boost circuits typically have a right-hand zero in their transfer functions in a continuous current mode, and thus resulting in poor performance in transient load response.

Another conventional technique for improving the converter performance is discussed in the thesis named “A Novel Voltage-boosting Converter: KY Converter.” FIG. 1 is a schematic diagram showing a topology of the KY converter. As shown in FIG. 1, the KY converter includes an input supply V_(IN), a switch M₁ with a body diode D₁, a switch M₂ with a body diode D₂, a diode D, an inductor L, capacitors C and C_(b), and a load R interconnected with one another.

In operation, when the switch M₁ is turned off and the switch M₂ is turned on, the input supply V_(IN), the diode D, the capacitor C_(b), and the switch M₂ form a current loop. The input supply V_(IN) provides power to the capacitor C_(b), causing the voltage across the capacitor C_(b) to reach V_(IN). Also, the input supply V_(IN), the diode D, the inductor L, the capacitor C, and the load form a current loop as well. The input supply V_(IN) provides power to the load R, as shown in FIG. 2( a). When the switch M₁ is turned on and the switch M₂ is turned off, the input supply V_(IN), the switch M₁, the capacitor C_(b), the inductor L, the capacitor C, and the load R form a current loop. The input supply V_(IN) and the capacitor C_(b) provide power to the load R, as shown in FIG. 2( b).

Even though the KY converter can have a low-ripple output voltage, a good noise rejection, and a fast load response, according to the thesis, the KY converter has a few drawbacks. For example, the output voltage V_(O) is in the range of V_(IN)˜2*V_(IN), so the KY converter can only function as a step-up, but not a step-down converter. In addition, when switches M₁ and M₂ are both turned off or inoperative, the input supply V_(IN) still supplies power to the load R through another current loop formed by the input supply V_(IN), the diode D, the inductor L, the capacitor C, and the load R. Thus the input voltage V_(IN) and the output voltage V_(O) can not be decoupled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a KY converter in accordance with the prior art.

FIG. 2( a) is a schematic diagram showing a current loop in the KY converter of FIG. 1 in one operating mode.

FIG. 2( b) is a schematic diagram showing a current loop in the KY converter of FIG. 1 in another operating mode.

FIG. 3 is a schematic diagram showing a converter in accordance with several embodiments of the disclosure.

FIG. 4 is a schematic diagram showing a converter in accordance with additional embodiments of the disclosure.

DETAILED DESCRIPTION OF THE INVENTION

Specific details of several embodiments of the disclosure are described below with reference to DC-DC converters and associated methods of operation. Moreover, several other embodiments of the converters may have different configurations, components, or procedures than those described in this section. A person of ordinary skill in the art, therefore, will accordingly understand that the converters and the associated methods of operation may have other embodiments with additional elements, or the invention may have other embodiments without several of the elements shown and described below with reference to FIGS. 3 and 4.

FIG. 3 is a schematic diagram showing a converter 100 in accordance with several embodiments of the disclosure. As shown in FIG. 3, the converter 100 includes an input port 101 for receiving an input voltage V_(IN); an output port 102 for providing an output signal V_(O); a first switch S₁ electrically coupled to the input port 101 at one terminal and coupled to ground via a second switch S₂ at the other terminal; the second switch S₂ electrically coupled between the other terminal of the first switch S₁ and ground; a third switch S₃ electrically coupled to the input port 101 at one terminal and coupled to the output port 102 via an inductor L₁ at the other terminal; the inductor L₁ electrically coupled between the other terminal of the third switch S₃ and the output port 102; a first capacitor C₁ electrically coupled between the first switch S₁ and the third switch S₃; an output capacitor C₂ electrically coupled between the output terminal and ground; and a load R_(L) coupled in parallel to the output capacitor C₂. The third switch S₃ can include transistors, MOSFET, IGBT, and/or other controllable devices except a diode.

When the output voltage is required to be between 0˜V_(IN), the first switch S₁ and the second switch S₂ are off or inoperative, and the third switch S₃ operates on a linear-active region or a saturated region (i.e., the switch status). The input V_(IN), the third switch S₃, the inductor L₁, the output capacitor C₂, and the load R_(L) form a current loop. The input V_(IN) provides power to the inductor L₁, the output capacitor C₂, and the load R_(L). When the third switch S₃ operates in the linear-active region, converter 100 acts as a low-dropout regulator. The output voltage V_(O) is controlled by adjusting the conduction voltage drop across the third switch S₃. When the third switch S₃ operates in the saturated region (i.e., the switch status), the output voltage V_(O) of the converter 100 is close to V_(IN).

When the output voltage is required to be between V_(IN)˜2*V_(IN), the first switch S₁, the second switch S₂, and the third switch S₃ are all in operation. Further, the second switch S₂ and the third switch S₃ are turned on or off simultaneously. The first switch S₁ and the second switch S₂ are turned on complementarily to each another. When the first switch S₁ is turned off and the second switch S₂ and the third switch S₃ are both turned on, the input V_(IN), the third switch S₃, the first capacitor C₁, and the second switch S₂ form a current loop. The input V_(IN) provides power to the first capacitor C₁, causing the voltage across the first capacitor C₁ to rise toward V_(IN). The input V_(IN), the third switch S₃, the inductor L₁, the output capacitor C₂, and the load R_(L) also form a current loop. The input V_(IN) provides power to the load R_(L). When the first switch S₁ is turned on and the second switch S₂ and the third switch S₃ are both turned off, the input V_(IN), the first switch S₁, the first capacitor C₁, the inductor L₁, the output capacitor C₂, and the load R_(L) form a current loop. Both the input V_(IN) and the first capacitor C₁ provide power to the load R_(L). The output voltage V_(O) is controlled by adjusting the duty cycle of the first switch S₁. As a result, the output voltage V_(O) can range between 0˜2*V_(IN). Also, the input port 101 and the output port 102 are coupled when the first switch S₁ or the third switch S₃ is on, and decoupled when both S₁ and S₃ are off.

FIG. 4 is a schematic diagram showing a converter 200 in accordance with additional embodiments of the disclosure. Common components and structures are identified by the same reference numbers in FIGS. 3 and 4. As shown in FIG. 4, the converter 200 includes a fourth switch S₄ coupled between one terminal of the third switch S₃ and ground. The fourth switch S₄ can include a diode, a transistor, a MOSFET, an IGBT, and/or other controllable devices.

When the output voltage V_(O) is required to be between 0˜V_(IN), the first switch S₁ and the second switch S₂ are both off, the third switch S₃ and the fourth switch S₄ are turned on complementarily to each other. When the third switch S₃ is turned on and the fourth switch S₄ is turned off, the input V_(IN), the third switch S₃, the inductor L₁, the output capacitor C₂ and the load R_(L) form a current loop. The input V_(IN) provides power to the inductor L₁, the output capacitor C₂ and the load R_(L). When the third switch S₃ is turned off and the fourth switch S₄ is turned on, the inductor L₁, the output capacitor C₂, the load R_(L) and the fourth switch S₄ form a current loop. The inductor L₁ and the output capacitor C₂ provide power to the load R_(L). The output voltage V_(O) is controlled by adjusting the duty cycle of the third switch S₃.

When the output voltage is required to be between V_(IN)˜2*V_(IN), the operation of converter 200 can be generally similar to that of the converter 100 of FIG. 3. The first switch S₁, the second switch S₂, and the third switch S₃ can be all in operation. Further, the second switch S₂ and the third switch S₃ are turned on or off simultaneously; the first switch S₁ and the second switch S₂ are turned on complementarily to each other; the fourth switch S₄ is off. When the first switch S₁ is turned off and the second switch S₂ and the third switch S₃ are both turned on, the input V_(IN), the third switch S₃, the inductor L₁, the output capacitor C₂, and the load R_(L) form a current loop. The input V_(IN) is supplied to the output capacitor C₂ and the load R_(L). When the first switch S₁ is turned on and the second switch S₂ and the third switch S₃ are both turned off, the input V_(IN), the first switch S₁, the first capacitor C₁, the inductor L₁, the output capacitor C₂ and the load R_(L) form a current loop. The input V_(IN) and the first capacitor C₁ provide power to the load R_(L). The output voltage V_(O) is controlled by adjusting the duty cycle of the first switch S₁.

Several embodiments of the converter 100 and the converter 200 can have improved transient load response performance than conventional converters. When the output voltage is between 0˜V_(IN), the load response performance of the converter 100 and the converter 200 are much better than that of a conventional buck converter.

Furthermore, the inductor L₁ side of the voltage “V” in the converter 100/200 is from less than V_(IN) (subtract the voltage drop of the third switch S₃ from V_(IN)) to 2*V_(IN). However, the inductor side of the voltage “V′” in conventional buck converter is from less than V_(IN) (subtract the voltage drop of the corresponding switch from V_(IN)) to V_(IN). When the load changes to a heavy load condition from a light load condition, the maximum of the inductor current rise rate of the conventional buck converter is (V′−V_(O))/L_(V), where L_(V) is the inductance of the corresponding inductor. In contrast, the maximum inductor current rise rate in the converter 100/200 is (V−V_(O))/L_(1(V)), where L_(1(V)) is the inductance of inductor L₁. As described above, the value of V is near twice of that of V′. Hence, when the converter 100/200 has the same inductance as in a conventional buck converter, i.e., L_(V)=L_(1(V)), (V−V_(O))/L_(1(V))>(V′−V_(O))/L_(V). As a result, the inductor current rise rate of the converter 100/200 is much faster than that of the conventional buck converter to improve the load response.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the invention. For example, many of the elements of one embodiment may be combined with other embodiments in addition to or in lieu of the elements of the other embodiments. Accordingly, the invention is not limited except as by the appended claims. 

1. A power converter, comprising: an input port configured to receive an input signal; an output port configured to provide an output signal; a first switch having a first terminal electrically coupled to the input port and a second terminal; a second switch having a third terminal electrically coupled to the second terminal of the first switch and a fourth terminal electrically coupled to ground; a third switch having a fifth terminal electrically coupled to the input port and a sixth terminal; an inductor electrically coupled between the sixth terminal of the third switch and the output port; a first capacitor electrically coupled between the second terminal of the first switch and the sixth terminal of the third switch; and a second capacitor electrically coupled between the inductor and ground.
 2. The power converter of claim 1, wherein the third switch includes at least one of a transistor, a MOSFET, and an IGBT.
 3. The power converter of claim 1, further comprising a fourth switch having one terminal electrically coupled between the sixth terminal of the third switch and ground.
 4. A power converter, comprising: a first switch; a second switch electrically coupled to the first switch in series, wherein the first switch being electrically coupled to a first node and to a second node via the second switch; a capacitor; and a third switch electrically coupled to the first node and to the second node via the capacitor and the second switch, the third switch having a linear-active region of operation.
 5. The power converter of claim 4, further comprising a fourth switch electrically coupled to the first node via the third switch and to the second node.
 6. The power converter of claim 4, further comprising a fourth switch electrically coupled to the first node via the third switch and to the second node, wherein the fourth switch includes at least one of a diode, a transistor, a MOSFET, and an IGBT.
 7. The power converter of claim 4, wherein the first and second nodes are first and second input nodes, and wherein the power converter further includes an inductor electrically coupled to the first input node via the third switch and to the first output node.
 8. The power converter of claim 4, wherein the first and second nodes are first and second input nodes and the capacitor is a first capacitor, and wherein the power converter further includes: an inductor electrically coupled to the first input node via the third switch and to the first output node; and a second capacitor electrically coupled to the first and second output nodes.
 9. A method for converting an input voltage to an output voltage, comprising receiving an input voltage at an input port, the input voltage having an input voltage value; achieving a first output voltage between zero and the input voltage value by (i) deactivating a first switch and a second switch and (ii) activating a third switch to form a first loop to provide the input voltage to an output port; and achieving a second output voltage between the input voltage value and about twice the input voltage value by (i) forming a second loop to provide the input voltage to charge a capacitor and (ii) by forming a third loop to provide the input voltage and storage energy in the capacitor to an output port.
 10. The method of claim 9, wherein achieving a first output voltage includes operating the third switch in a linear-active region of the third switch.
 11. The method of claim 9, wherein achieving a first output voltage includes operating the third switch in a saturated region of the third switch.
 12. The method of claim 9, wherein achieving a first output voltage includes forming the first loop with the third switch, an inductor, and an output capacitor.
 13. The method of claim 9, wherein achieving a second output voltage includes forming the second loop with the third switch, the capacitor, and the second switch.
 14. The method of claim 9, wherein achieving a second output voltage includes forming the third loop with the first switch, the capacitor, and the inductor. 